Faulty memory cells are inevitable in any practical integrated circuit comprising a significant amount of memory. The faulty cells are the result of the ever-increasing design constraints imposed on modern integrated circuits. Conventional methods of dealing with faulty memory cells are overly costly and/or impractical for many applications.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.